The present invention relates to a semiconductor device and a method of fabricating the same. More specifically, the present invention is directed to a semiconductor device having a trench isolation structure on a silicon on insulator (SOI) substrate and a method of fabricating the same.
Generally, as integration level of a semiconductor device increases, both RC delay time due to parasitic capacitance and power dissipation caused by junction leakage current are greatly increased. This affects adversely not only high-speed operation of the semiconductor device, but also low electric characteristic.
Fabricating methods of semiconductor devices are recently becoming increasingly dependant on silicon on insulator (SOI) techniques. The SOI techniques may minimize both the parasitic capacitance and the leakage current, thereby realizing semiconductor devices with high-speed/low-power characteristics. An SOI substrate is formed of a base substrate, a buried insulating layer, and a silicon layer that are sequentially stacked. Since a transistor on the SOI substrate includes its source/drain region that is in contact with the buried insulating layer thereunder, there may exist neither the junction capacitance nor the leakage current at a lower portion of the source/drain region. Consequently, both the junction capacitance and the leakage current are remarkably reduced as a whole except at a portion in contact with the channel region of the device. In addition, adjacent semiconductor devices are completely insulated from each other by both the buried insulating layer and a device isolation layer. This leads to improvement in a latch-up problem of a CMOS device, thereby permitting devices to be highly integrated.
Unfortunately, however, since the silicon layer on the buried insulating layer has a thickness of 1 xcexcm or less, in case that a conventional shallow trench isolation (STI) technique is applied to the SOI substrate, the silicon layer may suffer defects due to stress.
FIGS. 1 through 4 are cross-sectional views illustrating a conventional method of fabricating a trench isolation structure on an SOI substrate.
Referring to FIGS. 1 and 2, a buffer oxide layer and a hard mask layer are sequentially formed on an SOI substrate 106 that is formed of a base substrate 100, a buried insulating layer 102, and an upper silicon layer 104. The hard mask layer is normally made of silicon nitride. A photoresist pattern 112 is formed on the hard mask layer to expose a predetermined region of the hard mask layer. By using the photoresist pattern 112 as an etch mask, the hard mask layer, the buffer oxide layer, and the upper silicon layer are successively patterned to form a trench region 114. As a result, an upper silicon pattern 104, a buffer oxide pattern 108, and a hard mask pattern 110 are sequentially formed on the buried insulating layer 102. The upper silicon pattern 104 corresponds to an active region of the semiconductor device.
Referring to FIG. 3, sidewalls of the upper silicon pattern 104 suffer defects due to damage that occurs while the upper silicon layer is etched to forming the trench region 114. The resultant structure where the photoresist pattern 112 is removed is annealed in an oxygen ambient so as to cure the defects of the sidewalls of the upper silicon pattern 104. As a result, the sidewalls of the upper silicon pattern 104 are oxidized to form a trench oxide layer 116. A trench liner layer 118 is conformally formed on an entire surface of the resultant structure where the trench oxide layer 116 is formed.
Referring to FIG. 4, a device isolation layer is formed to fill the trench region 114 on an entire surface of the resultant structure where the trench liner layer 118 is formed. The device isolation layer is polished by chemical mechanical polishing (CMP) to form an insulating layer pattern 126 filling an inside of the trench region 114. The trench liner layer 118 covering a sidewall and a top of the hard mask pattern 110, the hard mask pattern 110, and the buffer oxide layer pattern 108 are successively etched to expose the active region and also form a nitride liner 118a surrounding the insulating layer pattern 126. The trench oxide layer 116, the nitride liner 118a, and the insulating layer pattern 126 form an isolation structure.
As described above, according to the conventional method, annealing is done to cure the etching damage that the sidewalls of the upper silicon pattern 104 suffers while forming the trench region 114. In the annealing step, atoms of oxygen are diffused into an interface between the upper silicon pattern 104 and the buried insulating layer 102, resulting in oxidation of a bottom edge of the upper silicon pattern 104. The oxidation of the silicon layer leads to formation of a silicon oxide layer, which is expanded about twice as much as the silicon layer. When the edge of the bottom of the upper silicon pattern 104 is oxidized, tensile stress is applied to the upper silicon pattern 104. This causes stress-induced defects to the upper silicon pattern 104. Unlike a transistor on a single crystalline silicon substrate, a transistor on an SOI substrate includes its source-drain region that is in contact with a buried insulating layer thereunder. In case of an SOI semiconductor device, a defect D of an upper edge of an active region causes improper operation of the device and also an increase in leakage current, as shown in FIG. 4. Therefore, it is imperative to develop a method for minimizing defects of the upper edge of the active region.
The present invention provides a semiconductor device having a trench isolation structure and a method of fabricating the same that can prevent a silicon layer from suffering tensile stress so as to reduce defects of an active region.
The present invention also provides a semiconductor device having a trench isolation structure and a method of fabricating the same that may minimize both leakage current and wmisoperation of the device.
According to the present invention, the semiconductor device comprises a trench region and an isolation structure. The trench region is disposed to define an active region at a predetermined region of a silicon on insulator (SOI) substrate formed by sequentially stacking a buried insulating layer and an upper silicon layer on a base substrate. The isolation structure fills an inside of the trench region. Shown by a cross-sectional view of the trench region, the trench region comprises a deep trench region and a shallow trench region. The deep trench region is where the silicon layer penetrates to the buried insulating layer and the shallow trench region exists at an outside of the deep trench region. That is, the trench region has a stepped sidewall. The isolation structure includes a trench oxide layer, a trench liner, and an insulating layer pattern. The trench oxide layer and the trench liner cover a bottom and a sidewall of the shallow trench region. The insulating layer pattern fills an inside of the trench region covered with the trench liner.
A method of fabricating the semiconductor device comprises sequentially forming a buffer oxide layer and a hard mask layer on an SOI substrate formed by sequentially stacking a buried insulating layer and an upper silicon layer on a base substrate. The hard mask layer, the buffer oxide layer, and the silicon layer of a predetermined depth are successively patterned to form a trench region in the upper silicon layer. A bottom and a sidewall of the trench region are thermally oxidized. A trench liner is formed to conformally cover the bottom and the sidewall of the trench region. The trench liner on the bottom of the trench region and the upper silicon layer are successively patterned to form a modified trench region. Shown by a cross-sectional view of the trench region, the modified trench region includes a deep trench region where the buried insulating layer is exposed and a shallow trench region existing at an outside of the deep trench region. An insulating layer pattern is formed to fill an inside of the modified trench region. Thereafter, the hard mask layer and the buffer oxide layer remaining on the upper silicon layer are removed.
The insulating layer pattern and the trench liner covering both the sidewall and bottom of the trench region correspond to a device isolation layer defining an active region.